I honestly think this is fundamentally impossible. Factory tech and Agile just don't mix. Failing in software is cheap, but with silicon, no matter how low the tape-out costs are, every failure costs you a massive amount of physical time. Also, open-source EDA tools are currently stuck on legacy nodes. Considering the huge gap with state-of-the-art nodes, why would anyone even bother?
Software monetization works because of scale-out. (The fatal flaw of SaaS is the endless pressure to update, completely ruining the idea of 'finished' software.) But hardware? Once it's taped out, it’s a physical endpoint that needs no maintenance. How are you supposed to charge a monthly subscription for that
To add to this: the downstream customers also hate change, just as much as people hate Windows updates. They much prefer being able to buy the same chip for 10 years.
(here at Medium-Size-Fabless-Semi-Inc, I'm in the middle of revving a bunch of parts that are about 10 years old, not because we want to add new features to them but because the process node is so obsolete it's becoming difficult to fab. Yes, they're getting new features, but that's not the primary driver of business)
On the other hand, because parts are physical objects, you can charge money for them. Piracy is .. not nonexistant (ask FTDI) but not a major concern.
There are some interesting corners for rapid-rev electronics, but there's a decision tree:
- can I do this with a microcontroller?
- if not, how about an FPGA?
- ok, there really is no alternative to ASIC, is the market size enough to support that?
Your perspective is much more refined than mine, and I'm learning a lot from it. You come across as a senior programmer in the exact same industrial equipment field as me. Thank you for taking the time to comment
Why couldn't a company committed to mask fabrication and wafer fabrication, in concept, perform these steps daily, or several times daily? Multiple prototype designs could be grouped together so multiple customers can realize a new design instance in the same iteration.
With an appropriate debug core in the same wafer, designers who'd completed a tape-out could connect to their chip well enough to repeat their design-verification tests on this real hardware, remotely even (no need to physically handle the device 'til you're certain it's working.) Once satisfied, customers could promote their design to be bonded out for installation into their PCB.
"Sure thing boss, we'll add an extra USART core to this afternoon's tape out."
The iteration cycles are limited necessarily by the time between tapeout and getting chips off the line to a testable state. Maybe there's a little room to get an in-wafer test probe system built at the fab if each die has a standard pad layout, which would speed up the 'testable state' part of that timeline. But if your timeline is weeks (if only!) to months, there's little utility in being able to make incremental changes on a daily basis.
Plus, the only way fab costs become achievable are MPW runs which don't have adequate demand for multiple daily runs. The ones I've used run a few processes each month, rotating between most of them on a bimonthly to quarterly basis. They just don't fill up fast enough. But I'm small time fabless so maybe I'm missing something.
Because you are dealing with the physical world where those different designs have different requirements that can conflict. It’s like saying all software is basically the same, why don’t you just abstract it all and run it on these Raspberry Pi’s.
You can do that, but it’s going to turn out poorly.
Accelerating the process is an incredibly obvious desire for literally everyone in the industry and there are already gobs of money being put into R&D.
The fact of the matter is that we're dealing with physical and chemical processes. It simply takes time for atoms to move across space. In many steps of the semiconductor fab process we are literally building up the chip by single-atom thick layers.
There's very finite limits to how fast you can throw atoms at a substrate. There are finite limits to how much time a photoresist must be exposed. There are finite limits to how fast chemicals can etch the surface. You can only saw a wafer so fast, you can only physically transport dice through space so fast.
These are problems that the entire industry wants to solve. These are problems at the bleeding edge of physics. This is not something a startup is going to solve, purely because you need to already have an entire semiconductor fab to iterate in.
Part of the delay is really just commercial. Fabs are optimized for utilization - throughput, not latency. A fab operator will prefer to queue up a load of work with as few gaps as possible, and your shuttle service run has to fit in one of the gaps. If you're NVIDIA and you've already booked the fab, there might not be so much delay. But not zero.
Just to buttress and embroider around your point that a fab is not a small business:
If there was a realistic way even to go from bare wafers to non-trivial custom chips in a small-batch fashion, you can bet there would be a cottage industry around it. I would love to live in a world where I could manufacture custom silicon as easily as I can manufacture a custom PCB or custom mechanical part.
But as it stands, quick-turn, rapid-proto "micro" fabs are obscenely expensive, to the extent that if you aren't absolutely certain you need the performance gains from custom silicon, justified by years of R&D that confirms the inadequacy of a multi-chip solution, then the idea is killed before any layout engineer is contacted.
Microfabs are either operated by research institutes, or they're booked solid for years, and basically printing money.
> Multiple prototype designs could be grouped together
They do this, it's called a multi-project wafer (it's on Wikipedia). It doesn't help with lead time of course. As far as I know tape-out cost is a lot cheaper (if your design is microcontroller-scale) but still in the $100k+ region.
I sort of expected this to happen with tightly coupled customer-customizable chiplets inside a single package, instead. But it seems that packaging is also better left to Intel and AMD, I guess.
Regarding hardware, it's not entirely true that it doesn't need maintenance/development. See "stepping" https://en.wikipedia.org/wiki/Stepping_level. There are sometimes ways to tweak the masks to fix a "silicon bug".
Yes, but that still costs significant money in a way that software deployment doesn't. IME most chips get maybe one or two metal layer revisions then a rev B consolidated bugfix - and then get left alone.
Yeah, my experience has been exactly that. And the person paying the bills will try as hard as possible to avoid/delay a metal rev as possible because they’re expensive and time consuming so they blow up the schedule if you can’t release the chip with rev. A.
One place I worked at did fast iteration by pushing as much of the risk as they could off the silicon and by using several distinct ASICs instead of a single monolithic one which would have had better performance on its own. Gave them the ability to rev the different parts at the rate they needed it at a cost to software complexity and hardware compatibility and cost.
I honestly think this is fundamentally impossible. Factory tech and Agile just don't mix. Failing in software is cheap, but with silicon, no matter how low the tape-out costs are, every failure costs you a massive amount of physical time. Also, open-source EDA tools are currently stuck on legacy nodes. Considering the huge gap with state-of-the-art nodes, why would anyone even bother? Software monetization works because of scale-out. (The fatal flaw of SaaS is the endless pressure to update, completely ruining the idea of 'finished' software.) But hardware? Once it's taped out, it’s a physical endpoint that needs no maintenance. How are you supposed to charge a monthly subscription for that
To add to this: the downstream customers also hate change, just as much as people hate Windows updates. They much prefer being able to buy the same chip for 10 years.
(here at Medium-Size-Fabless-Semi-Inc, I'm in the middle of revving a bunch of parts that are about 10 years old, not because we want to add new features to them but because the process node is so obsolete it's becoming difficult to fab. Yes, they're getting new features, but that's not the primary driver of business)
On the other hand, because parts are physical objects, you can charge money for them. Piracy is .. not nonexistant (ask FTDI) but not a major concern.
There are some interesting corners for rapid-rev electronics, but there's a decision tree:
Your perspective is much more refined than mine, and I'm learning a lot from it. You come across as a senior programmer in the exact same industrial equipment field as me. Thank you for taking the time to comment
I find it ironic how different the culture is between software and hardware people. This makes me very happy about my decision of going into software
Why couldn't a company committed to mask fabrication and wafer fabrication, in concept, perform these steps daily, or several times daily? Multiple prototype designs could be grouped together so multiple customers can realize a new design instance in the same iteration.
With an appropriate debug core in the same wafer, designers who'd completed a tape-out could connect to their chip well enough to repeat their design-verification tests on this real hardware, remotely even (no need to physically handle the device 'til you're certain it's working.) Once satisfied, customers could promote their design to be bonded out for installation into their PCB.
"Sure thing boss, we'll add an extra USART core to this afternoon's tape out."
The iteration cycles are limited necessarily by the time between tapeout and getting chips off the line to a testable state. Maybe there's a little room to get an in-wafer test probe system built at the fab if each die has a standard pad layout, which would speed up the 'testable state' part of that timeline. But if your timeline is weeks (if only!) to months, there's little utility in being able to make incremental changes on a daily basis.
Plus, the only way fab costs become achievable are MPW runs which don't have adequate demand for multiple daily runs. The ones I've used run a few processes each month, rotating between most of them on a bimonthly to quarterly basis. They just don't fill up fast enough. But I'm small time fabless so maybe I'm missing something.
Because you are dealing with the physical world where those different designs have different requirements that can conflict. It’s like saying all software is basically the same, why don’t you just abstract it all and run it on these Raspberry Pi’s.
You can do that, but it’s going to turn out poorly.
The wafer manufacturing process takes weeks to months after a tape out.
Accelerating this process sounds like a good focus for an SBIR (small business innovation research) RFP.
Accelerating the process is an incredibly obvious desire for literally everyone in the industry and there are already gobs of money being put into R&D.
The fact of the matter is that we're dealing with physical and chemical processes. It simply takes time for atoms to move across space. In many steps of the semiconductor fab process we are literally building up the chip by single-atom thick layers.
There's very finite limits to how fast you can throw atoms at a substrate. There are finite limits to how much time a photoresist must be exposed. There are finite limits to how fast chemicals can etch the surface. You can only saw a wafer so fast, you can only physically transport dice through space so fast.
These are problems that the entire industry wants to solve. These are problems at the bleeding edge of physics. This is not something a startup is going to solve, purely because you need to already have an entire semiconductor fab to iterate in.
A fab is not a small business!
Part of the delay is really just commercial. Fabs are optimized for utilization - throughput, not latency. A fab operator will prefer to queue up a load of work with as few gaps as possible, and your shuttle service run has to fit in one of the gaps. If you're NVIDIA and you've already booked the fab, there might not be so much delay. But not zero.
Nice little backgrounder: https://siliconmasters.co/blogs/our-blog/how-photomasks-for-...
Just to buttress and embroider around your point that a fab is not a small business:
If there was a realistic way even to go from bare wafers to non-trivial custom chips in a small-batch fashion, you can bet there would be a cottage industry around it. I would love to live in a world where I could manufacture custom silicon as easily as I can manufacture a custom PCB or custom mechanical part.
But as it stands, quick-turn, rapid-proto "micro" fabs are obscenely expensive, to the extent that if you aren't absolutely certain you need the performance gains from custom silicon, justified by years of R&D that confirms the inadequacy of a multi-chip solution, then the idea is killed before any layout engineer is contacted.
Microfabs are either operated by research institutes, or they're booked solid for years, and basically printing money.
> Fabs are optimized for utilization - throughput, not latency
I remember hearing some company trying for the speed
The time from tapeout to first samples is 3-4 months even for the biggest customers of TSMC.
Shorter for a metal only change.
> A fab is not a small business!
An SBIR is just a cost effective way for the government to put a number of PhDs/engineers to work on a problem.
> Multiple prototype designs could be grouped together
They do this, it's called a multi-project wafer (it's on Wikipedia). It doesn't help with lead time of course. As far as I know tape-out cost is a lot cheaper (if your design is microcontroller-scale) but still in the $100k+ region.
I sort of expected this to happen with tightly coupled customer-customizable chiplets inside a single package, instead. But it seems that packaging is also better left to Intel and AMD, I guess.
Regarding hardware, it's not entirely true that it doesn't need maintenance/development. See "stepping" https://en.wikipedia.org/wiki/Stepping_level. There are sometimes ways to tweak the masks to fix a "silicon bug".
Yes, but that still costs significant money in a way that software deployment doesn't. IME most chips get maybe one or two metal layer revisions then a rev B consolidated bugfix - and then get left alone.
Yeah, my experience has been exactly that. And the person paying the bills will try as hard as possible to avoid/delay a metal rev as possible because they’re expensive and time consuming so they blow up the schedule if you can’t release the chip with rev. A.
One place I worked at did fast iteration by pushing as much of the risk as they could off the silicon and by using several distinct ASICs instead of a single monolithic one which would have had better performance on its own. Gave them the ability to rev the different parts at the rate they needed it at a cost to software complexity and hardware compatibility and cost.
How do you build a company on something that's free? Daniel Schultz, founder of aesc silicon explains.
How do you build a tourism business when anyone can walk into the woods for free?