And if you are curious about the modern radiation hardened CPUs then the current state of the art ones are the MOOG BRE440 [0] and the BAE RAD5500 [1], 5545 [2] being the highest performance multi core one.
Even more interesting that they both use the IBM POWER architecture!
There have been a number of rad-hard SPARC chips from different vendors tthat have flown along the way, and I know Frontgrade/Gaisler currently sells a SPARC v8 version, which isn't that far behind the 'state of the art' as the e5500 based PPCs from BEA (at least as far as state of the art in space rated, rad-hard processors goes...it's a conservative market). Quite a few rad-hard ARMs out there farther down the performance curve.
Frontgrade also advertises a rad-hard RISC-V, as does Microchip (a PIC64 variant), that I know nothing about, but seems like an inevitable next step. Seems like you could grab some Xilinx rad-hard FPGA and bobs your uncle.
> Back in the late 1970’s and early 1980’s Sandia National Laboratory (in Albuquerque NM USA) began building the capacity to design, fab, and test IC’s at scale (packaging was handled by Fairchild and Allied Signal).
We need more of this kind of thing, generally: government agencies building up in-house technical capability, instead of outsourcing everything to contractors.
For instance: there should be a government-controlled pharmaceutical manufacturer of last resort. The clear benefits would be to provide extra capacity and prevent things like Martin Shkreli's scams with Retrophin/Turing Pharmaceuticals (https://en.wikipedia.org/wiki/Martin_Shkreli#Thiola_price_hi...).
Very interesting! Definitely some jargon I’ve not come across before.
“The chips were made on a n-on-n+ epitaxial substrate to provide latchup control, extensive guard rings around transistors were used and hardened oxides”
This is standard semiconductor manufacturing jargon.
"Substrate" here refers to the silicon wafer on which the integrated circuits are made, which at the end of the manufacturing process is cut into individual chips, which are then packaged as CPUs in this case.
An epitaxial wafer is a wafer on which epitaxial growth has been done before the rest of the manufacturing process. The wafers are cut from a huge crystal that has been grown from molten silicon. Initially they have a uniform concentration of doping impurities throughout their volume.
Epitaxial growth means that an extra layer of silicon is grown on the wafer and the growth is done in such a manner that all the layer is a single crystal and its lattice continues the crystal of the wafer, without interface defects.
The purpose is to have a different concentration of impurities in the extra layer, compared with the base wafer. N-on-n+ means that the initial wafer contained N-doping impurities, e.g. antimony, in a very high concentration (+), so that its electrical resistance would be minimum, while the "n" epitaxial layer also contains an N-doping impurity, e.g. phosphorus, but in a much lower concentration, so that it has a high electrical resistivity.
Both the fabrication of silicon wafers and the epitaxial growth are typically done by other companies than those that make integrated circuits, so the IC maker, or a silicon foundry like TSMC, buys epitaxial wafers according to a certain specification and they use them as the starting material in their manufacturing process.
"Latchup control" is a term specific to CMOS integrated circuits. In CMOS there exists a parasitic thyristor (a.k.a. SCR) composed of 2 parasitic bipolar transistors. If the parasitic thyristor turns on, it applies a short-circuit on the power supply, causing a huge electrical current spike, which normally destroys the integrated circuit, perhaps also other things if the power supply is not protected against short circuits.
In order to prevent the latchup of the parasitic thyristor, the structure is modified in various ways to reduce the gain of the parasitic transistors. If the gain is low enough, the thyristor cannot turn on.
Using a simple n substrate (which is cheaper) results in a high gain for the parasitic pnp bipolar transistor. Using an epitaxial n-on-n+ wafer reduces the gain of the pnp, lowering the probability of latchup.
Guard rings around transistors (which are made by diffusing certain doping impurities and then possibly also covering the diffused ring with a polysilicon or metal ring) have various purposes, typically related to preventing the electrical breakdown of the transistors at lower voltages than intended. This is especially important for radiation-hardened devices, because the most frequent effect of the passage of a ionizing particle through the semiconductor would be to generate mobile charge carriers that could cause the electrical breakdown of a transistor.
"Hardened oxide" is a more ambiguous term, but I assume that here it refers to high-quality oxide, i.e. which has a high value for the electrical field that can be sustained without electrical breakdown.
Interesting combination of 'remarkable' and 'wtf' that we fling nuclear weapons around with the computational equivalent of a couple of TRS-80s[1]. I can only imagine the sighs of relief from the devs when things like the MIL-STD-1750a and later rad-hard SPARC and PPC variants came along.
[1] yes...I know the TRS-80 had a z80, not an 8085. Close enough.
On the flip side, the fact that those processors were enough to steer spacecraft make me feel like there’s also a decent amount of remarkable wtf in how much compute we have now and how little we get out of each instruction on average compared to what people were doing with these z80 equivalents.
When you don't have the overhead of an operating system with decades of backward compatibility cruft, a scheduler, a virtual memory controller, and a file system you can accomplish amazing things with simple processors. Bare metal is something I'd encourage every programmer to try.
I actually have a 8085 Primer Trainer that I built/used in the 90s for school. [1]
Programmed with pushbuttons and 7 segment LEDs. No backup memory so if you shut it off it lost it's program and you had to start over.
Not a programmer by trade, I prefer hardware...had no idea until recently how valuable the training was. We learned BASIC and 8085 machine code as well as building logic circuits from discrete parts. Then I used basically no code myself for 15 years until I learned Arduino.
Knowing the basics certainly helped me know what was going on. From there it was just syntax for languages.
Yeah exactly, we now have so many layers of stuff. On top of vmem & OS, add high def displays, and today’s corporate firewall and malware scanning. I wouldn’t be surprised if just booting my Win 11 laptop, logging in, and launching Teams uses more compute than the entire Galileo mission used over its entire 8 year run. :P
Even without the layers & cruft though, the raw perf is astounding to those of us who remember 8 bit 1Mhz microprocessors. Today’s gamers are used to double-digit teraflops(!) of compute, just to render all the pixels for Minecraft or Fortnite.
I don’t know if there’s a better way these days, but for me Arduino has been an easy & super fun way to futz with a tiny bare metal microprocessor.
Even hypersonic weapons with precision terminal guidance use truly ancient CPUs. Physics limits of molecular materials places a very low upper bound on the amount of compute required.
The rate at which an object in the physical world can alter its trajectory is ultimately limited by the strength of molecular bonds in the material it is made from. Exceed that limit and the object will disintegrate. This upper bound is extremely slow from the perspective of a CPU, making it computationally trivial. A computer can react orders of magnitude faster than the quickest physical objects.
I imagine you're correct about course correction speed, although I'd also expect that the materials and their properties are quite classified at present.
I would also imagine that there could be processing necessary that is mostly unrelated to manoeuvering speed (inlet/control surface management, etc). Perhaps some hypersonic experts could weigh in and let us know :)
If this was copy-pasted, isn't it much more likely that it was copy-pasted from a document describing the performance of the SA3000 chip, than from a document that was written before the SA3000 was developed?
The only overlap from the document with the text you quote is the "106", which is a pretty common mis-formatting issue.
Bad typesetting just indicates poor editing, not slop IMHO.
I guessed after about a second of thought that this actually meant 10^6. If I had to guess how this happened, somebody just wrote their prose in Word with the 6 in superscript and cut and paste it into HTML which lost the formatting.
I think it's a shame if you consider the whole article (which I personally found very interesting) as slop because of 2 incorrectly formatted numbers that could easily result from a cut-and-paste error. It's clear the article hadn't been well proof read as there are a number of spelling mistakes too, but that doesn't make the content itself slop.
Like others have mentioned, 50k small CPUs like 8085 can be made in a single production batch (i.e. a small basket containing silicon wafers, which passes through all manufacturing steps), so a number like this is likely to be the minimum amount that can be produced.
The customer would order this minimum quantity, and most of it will probably be kept as spares.
That number was probably shaped by minimum production-run requirements, alongside the need for software development units, along with other factors, like the use in Trident II and other quests we may not know about.
There isn't really a minimum production run for silicon chips, they do small test runs all the time to test new designs.
At least not from a practical perspective.
From an economic perspective, stopping after a single small run is just wasteful. The upfront design costs are so high, and the per wafer costs are so slow that you might as well make a lot extra. Maybe you can find a use for them, or sell them to someone else.
Trident 2 (article says used 8 of these chips), and google says around 400-424 made, so easily would have soaked up 4000 of these CPUs with spares alone. So if anything, the production run seems light.
I read they had their own fab, so the minimum production run aspect would appear moot.
I assume the tooling and process are such that it’s a one-time thing, as in, this is the most of these chips that we could ever possibly need for all time. They’re not going to be able to spin up the same fab and build the same chips the same way again in the future whether that’s 5 or 50 years in the future. Given the long lifespans of military systems, it’s maybe not so crazy.
And if you are curious about the modern radiation hardened CPUs then the current state of the art ones are the MOOG BRE440 [0] and the BAE RAD5500 [1], 5545 [2] being the highest performance multi core one.
Even more interesting that they both use the IBM POWER architecture!
0, https://www.moog.com/products/avionics/spacecraft-avionics/b...
1, https://en.wikipedia.org/wiki/RAD5500
2, https://web.archive.org/web/20190226111129/https://www.baesy...
There have been a number of rad-hard SPARC chips from different vendors tthat have flown along the way, and I know Frontgrade/Gaisler currently sells a SPARC v8 version, which isn't that far behind the 'state of the art' as the e5500 based PPCs from BEA (at least as far as state of the art in space rated, rad-hard processors goes...it's a conservative market). Quite a few rad-hard ARMs out there farther down the performance curve.
Frontgrade also advertises a rad-hard RISC-V, as does Microchip (a PIC64 variant), that I know nothing about, but seems like an inevitable next step. Seems like you could grab some Xilinx rad-hard FPGA and bobs your uncle.
what scale of radiation do such hardened designs target?
1 Megarad (10 Kilogray)
In comparison radtherapy patients get 20 gray in 1-2 weeks so it's the 20/10000 = 0.02% of what these designs target
Expanding a wee bit on what the other guy said, that's typically 20Gy *one Gray at a time*.
A whole body exposure of 5Gy would kill you, although it would happen over two weeks.
10kGy? Spectacularly fatal.
Wow, until you posted this I thought Moog was just a synthesizer company. And a bit of an odd one at that based on how I saw that synth presented.
Cousins. One made synths the other flight controls.
> Back in the late 1970’s and early 1980’s Sandia National Laboratory (in Albuquerque NM USA) began building the capacity to design, fab, and test IC’s at scale (packaging was handled by Fairchild and Allied Signal).
We need more of this kind of thing, generally: government agencies building up in-house technical capability, instead of outsourcing everything to contractors.
For instance: there should be a government-controlled pharmaceutical manufacturer of last resort. The clear benefits would be to provide extra capacity and prevent things like Martin Shkreli's scams with Retrophin/Turing Pharmaceuticals (https://en.wikipedia.org/wiki/Martin_Shkreli#Thiola_price_hi...).
Sandia is operated by a government contractor (Honeywell)
> instead of outsourcing everything to contractors.
But then how will politicians favor their campaign donors?
Very interesting! Definitely some jargon I’ve not come across before.
“The chips were made on a n-on-n+ epitaxial substrate to provide latchup control, extensive guard rings around transistors were used and hardened oxides”
This is standard semiconductor manufacturing jargon.
"Substrate" here refers to the silicon wafer on which the integrated circuits are made, which at the end of the manufacturing process is cut into individual chips, which are then packaged as CPUs in this case.
An epitaxial wafer is a wafer on which epitaxial growth has been done before the rest of the manufacturing process. The wafers are cut from a huge crystal that has been grown from molten silicon. Initially they have a uniform concentration of doping impurities throughout their volume.
Epitaxial growth means that an extra layer of silicon is grown on the wafer and the growth is done in such a manner that all the layer is a single crystal and its lattice continues the crystal of the wafer, without interface defects.
The purpose is to have a different concentration of impurities in the extra layer, compared with the base wafer. N-on-n+ means that the initial wafer contained N-doping impurities, e.g. antimony, in a very high concentration (+), so that its electrical resistance would be minimum, while the "n" epitaxial layer also contains an N-doping impurity, e.g. phosphorus, but in a much lower concentration, so that it has a high electrical resistivity.
Both the fabrication of silicon wafers and the epitaxial growth are typically done by other companies than those that make integrated circuits, so the IC maker, or a silicon foundry like TSMC, buys epitaxial wafers according to a certain specification and they use them as the starting material in their manufacturing process.
"Latchup control" is a term specific to CMOS integrated circuits. In CMOS there exists a parasitic thyristor (a.k.a. SCR) composed of 2 parasitic bipolar transistors. If the parasitic thyristor turns on, it applies a short-circuit on the power supply, causing a huge electrical current spike, which normally destroys the integrated circuit, perhaps also other things if the power supply is not protected against short circuits.
In order to prevent the latchup of the parasitic thyristor, the structure is modified in various ways to reduce the gain of the parasitic transistors. If the gain is low enough, the thyristor cannot turn on.
Using a simple n substrate (which is cheaper) results in a high gain for the parasitic pnp bipolar transistor. Using an epitaxial n-on-n+ wafer reduces the gain of the pnp, lowering the probability of latchup.
Guard rings around transistors (which are made by diffusing certain doping impurities and then possibly also covering the diffused ring with a polysilicon or metal ring) have various purposes, typically related to preventing the electrical breakdown of the transistors at lower voltages than intended. This is especially important for radiation-hardened devices, because the most frequent effect of the passage of a ionizing particle through the semiconductor would be to generate mobile charge carriers that could cause the electrical breakdown of a transistor.
"Hardened oxide" is a more ambiguous term, but I assume that here it refers to high-quality oxide, i.e. which has a high value for the electrical field that can be sustained without electrical breakdown.
Interesting combination of 'remarkable' and 'wtf' that we fling nuclear weapons around with the computational equivalent of a couple of TRS-80s[1]. I can only imagine the sighs of relief from the devs when things like the MIL-STD-1750a and later rad-hard SPARC and PPC variants came along.
[1] yes...I know the TRS-80 had a z80, not an 8085. Close enough.
On the flip side, the fact that those processors were enough to steer spacecraft make me feel like there’s also a decent amount of remarkable wtf in how much compute we have now and how little we get out of each instruction on average compared to what people were doing with these z80 equivalents.
When you don't have the overhead of an operating system with decades of backward compatibility cruft, a scheduler, a virtual memory controller, and a file system you can accomplish amazing things with simple processors. Bare metal is something I'd encourage every programmer to try.
I actually have a 8085 Primer Trainer that I built/used in the 90s for school. [1] Programmed with pushbuttons and 7 segment LEDs. No backup memory so if you shut it off it lost it's program and you had to start over.
Not a programmer by trade, I prefer hardware...had no idea until recently how valuable the training was. We learned BASIC and 8085 machine code as well as building logic circuits from discrete parts. Then I used basically no code myself for 15 years until I learned Arduino. Knowing the basics certainly helped me know what was going on. From there it was just syntax for languages.
[1] https://flic.kr/p/2mkG7gC
Yeah exactly, we now have so many layers of stuff. On top of vmem & OS, add high def displays, and today’s corporate firewall and malware scanning. I wouldn’t be surprised if just booting my Win 11 laptop, logging in, and launching Teams uses more compute than the entire Galileo mission used over its entire 8 year run. :P
Even without the layers & cruft though, the raw perf is astounding to those of us who remember 8 bit 1Mhz microprocessors. Today’s gamers are used to double-digit teraflops(!) of compute, just to render all the pixels for Minecraft or Fortnite.
I don’t know if there’s a better way these days, but for me Arduino has been an easy & super fun way to futz with a tiny bare metal microprocessor.
Even hypersonic weapons with precision terminal guidance use truly ancient CPUs. Physics limits of molecular materials places a very low upper bound on the amount of compute required.
The rate at which an object in the physical world can alter its trajectory is ultimately limited by the strength of molecular bonds in the material it is made from. Exceed that limit and the object will disintegrate. This upper bound is extremely slow from the perspective of a CPU, making it computationally trivial. A computer can react orders of magnitude faster than the quickest physical objects.
I imagine you're correct about course correction speed, although I'd also expect that the materials and their properties are quite classified at present.
I would also imagine that there could be processing necessary that is mostly unrelated to manoeuvering speed (inlet/control surface management, etc). Perhaps some hypersonic experts could weigh in and let us know :)
> I can only imagine the sighs of relief from the devs when things like the MIL-STD-1750a and later rad-hard SPARC and PPC variants came along.
What, so that they can debug in Chrome and put the fusing and inertial navigation processes in isolated web views?
You don't need much calculation power to manage a 30-min ballistic trajectory.
The inertial navigation system is the very crazy part, along with the nuclear fusion warhead design itself.
https://youtu.be/AazmxNs5kmE?is=2LE2q3rBSWDyTs7j
I was under the impression that the Trident II could do terminal phase maneuvering, so not a straight ballistic trajectory, but fair enough.
It controls the fusing, not positioning.
https://thebulletin.org/2017/03/how-us-nuclear-force-moderni...
> [1] yes...I know the TRS-80 had a z80, not an 8085. Close enough.
Clearly you meant the TRS-80 Model 100.
This is slop, but perhaps the old-fashioned kind.
> An 8085 processor that could handle 1×106 rads of radiation with only a 25% reduction in performance, and 3×106 rads with a 40% drop.
Hmm, from where did they copy-paste this mangled scientific notation?
Ah here we are, pg. 37 (46 in PDF file): https://apps.dtic.mil/sti/tr/pdf/ADA063902.pdf
If this was copy-pasted, isn't it much more likely that it was copy-pasted from a document describing the performance of the SA3000 chip, than from a document that was written before the SA3000 was developed?
The only overlap from the document with the text you quote is the "106", which is a pretty common mis-formatting issue.
Excellent find. And yes, obviously this is slop. 106 rad is exactly nothing for nuclear usage.
Bad typesetting just indicates poor editing, not slop IMHO.
I guessed after about a second of thought that this actually meant 10^6. If I had to guess how this happened, somebody just wrote their prose in Word with the 6 in superscript and cut and paste it into HTML which lost the formatting.
I think it's a shame if you consider the whole article (which I personally found very interesting) as slop because of 2 incorrectly formatted numbers that could easily result from a cut-and-paste error. It's clear the article hadn't been well proof read as there are a number of spelling mistakes too, but that doesn't make the content itself slop.
Yeah, but 318 should probably suffice.
> Galileo space probe [..] How many IC’s were needed? Over 50,000 for the probe itself, backups, testing chips etc.
I seriously doubt you need to fabricate 50k CPUs for a single space probe, including backups, testing chips, etc.
Like others have mentioned, 50k small CPUs like 8085 can be made in a single production batch (i.e. a small basket containing silicon wafers, which passes through all manufacturing steps), so a number like this is likely to be the minimum amount that can be produced.
The customer would order this minimum quantity, and most of it will probably be kept as spares.
That number was probably shaped by minimum production-run requirements, alongside the need for software development units, along with other factors, like the use in Trident II and other quests we may not know about.
There isn't really a minimum production run for silicon chips, they do small test runs all the time to test new designs.
At least not from a practical perspective.
From an economic perspective, stopping after a single small run is just wasteful. The upfront design costs are so high, and the per wafer costs are so slow that you might as well make a lot extra. Maybe you can find a use for them, or sell them to someone else.
Trident 2 (article says used 8 of these chips), and google says around 400-424 made, so easily would have soaked up 4000 of these CPUs with spares alone. So if anything, the production run seems light.
I read they had their own fab, so the minimum production run aspect would appear moot.
> other quests we may not know about.
Back then an interface between terrestrial computer systems and a Zeta Reticulan spacecraft required a small supercomputer on our side.
Wait for 99% of HN to totally not get the context of this
I assume the tooling and process are such that it’s a one-time thing, as in, this is the most of these chips that we could ever possibly need for all time. They’re not going to be able to spin up the same fab and build the same chips the same way again in the future whether that’s 5 or 50 years in the future. Given the long lifespans of military systems, it’s maybe not so crazy.
I also am curious about that statement. Seems something got mixed up between the quantity of the full run and the quantity for the probe.